1. Field of the Invention
This invention relates to a semiconductor memory device and a power supply control IC for use with a semiconductor memory device, and more particularly, to a portable-type semiconductor memory device backed up by a battery and the power control IC for use with a battery backed semiconductor memory device.
2. Description of the Related Art
FIG. 8 is a block diagram showing a known portable-type semiconductor memory device bearing a volatile semiconductor memory that needs battery backup. As shown in FIG. 8, the known portable-type semiconductor memory device 1 is connected to a host apparatus 2 via a connector, and is used as a data storage medium for the host apparatus 2. Typically available as an example of the portable-type semiconductor memory device 1 is a memory card that is a card-like data storage medium. As shown in FIG. 8, a memory 3 is provided for storing data and the like. The memory 3 is connected to the host apparatus 2 over a bus 7, through which data is exchanged, through the connector (not shown). The bus 7 is constructed of a data bus, an address bus, a control bus and the like, and over these buses, the host apparatus 2 sends a variety of data DATA, address data ADD, and a control signal CS and the like to the memory 3, and data stored in the memory 3 are accessed. Since the memory 3 is constructed of a volatile semiconductor memory such as an SRAM, power must be always supplied to it to hold data (for data backup). During use, the power supply VCC of the host apparatus 2 feeds, via a power supply line 100, power that is internally consumed by the portable-type semiconductor memory device 1 including the memory 3. When the portable-type semiconductor memory device 1 is disconnected from the host apparatus 2, power from the power supply VCC of the host apparatus 2 is interrupted. To prepare for power interruption, the portable-type semiconductor memory device 1 has, as internal power supplies, a first battery BAT 1 as its main battery and a second battery BAT 2 as its auxiliary battery.
Shown in FIG. 8 are: an external power supply voltage node 101 serving as a host apparatus power supply voltage node connected via the connector to the power supply line 100; an internal power supply voltage node 8 for supplying internally power to the internal circuit of the portable-type semiconductor memory device 1 including the memory 3; a main battery power supply voltage node 102 for receiving main battery power from the first battery BAT 1; an auxiliary battery power supply voltage node 103 for receiving auxiliary battery power from the second battery BAT 2; and a connection node 104 to which the output node of a voltage comparator 5 to be described later is connected.
The external power supply voltage node 101 is connected to the internal power supply voltage node 8 via a switch SW1 to be described later. The main battery power supply voltage node 102 and auxiliary battery power supply node 103 are arranged in parallel between the connection node 106 and ground node. The connection node 106 is connected to the internal power supply voltage node 8 via a switch SW2 to be described later. The memory 3 is powered via the internal power supply voltage node 8 from the power supply VCC in the host apparatus 2 as the external power supply or from the internal power supply, namely the first battery BAT 1 and the second battery BAT 2, thereby the memory 3 holds data. The first battery BAT 1 comprises a non-rechargeable primary battery such as a button battery, and the second battery BAT 2 comprises a rechargeable secondary battery. As shown in FIG. 8, R3 is connected between the connection node 106 and the switch SW2 and works as a protective resistor for controlling reverse current and is used commonly for both the first battery BAT 1 and second battery BAT 2. A protective diode D1 is connected between the connection node 106 and the main battery power supply voltage node 102 for preventing reverse current.
When a rechargeable secondary battery is used as the main battery or auxiliary battery, no battery replacement is required. A secondary battery, however, ages in performance through repeated charge and recharge cycles, prolonged storage periods, and environmental factors (high temperatures, temperature cycles, and the like), and is problematic in terms of reliability. Therefore, using the secondary battery as the main battery is not recommended. In view of this, a primary battery needing replacement is typically used as the main battery BAT 1. The second battery BAT 2 is provided to back up the memory 3 for data holding during replacement of the first battery BAT 1. Since the second battery BAT 2 is consumed during a brief period of time only for the replacement of the first battery BAT 1, the second battery BAT 2 may be a small-capacity battery and further may be a rechargeable secondary battery that needs no replacement. In the known semiconductor memory device 1 depicted in FIG. 8, the first battery BAT 1 serves also as a charging power supply for the second battery BAT 2.
Since the first battery BAT 1 is supposed to be replaced, the known portable-type semiconductor memory device 1 is provided with a detachable battery holder (not shown). Although the second battery BAT 2 theoretically needs no replacement, the known portable-type semiconductor memory device 1 employs a chemical battery, that in practice has limited charge and discharge cycles. The chemical battery is typically limited to hundreds of charge and discharge cycles. Furthermore, as already described, the battery ages in performance under operating and environmental conditions and sometimes battery liquid leakage occurs. In view of the above, the known portable-type semiconductor memory device 1 is also provided with the battery holder (not shown) for the second battery BAT 2 so that the second battery BAT 2 may be also replaced.
As already described, two switches SW1 and SW2 are provided to switch between the power supply VCC in the host apparatus 2 as the external power supply and the internal power supply of the first battery BAT 1 and second battery BAT 2. When the switch SW1 is on, the power supply VCC in the host apparatus 2 feeds power to the memory 3 via the internal power supply voltage node 8, and when the switch SW2 is on, the first battery BAT 1 and second battery BAT 2 feed power to the internal power supply voltage node 8. Also provided are a reference voltage generator circuit 4 for generating a reference voltage Vref, and resistors and R2 which are connected in series between the external power supply voltage node 101 and the ground node for giving at a connection node 105 of the resistors R1 and R2 a voltage responsive to the supply voltage supplied at the external power supply voltage node 101. A voltage comparator 5 which is driven by the supply voltage supplied at the external power supply voltage node 101 via the power supply line 100 by the host apparatus 2 is also provided as shown in FIG. 8. The voltage comparator 5 has one input node connected to the connection node 105 and the other input node for receiving the reference voltage Vref from the reference voltage generator circuit 4. The voltage comparator 5 outputs a signal VCOM that instructs to use the external power supply voltage when the voltage appearing at the node 105 is higher than the reference voltage Vref, and instructs to use the internal power supply voltage when the voltage appearing at the node 105 is lower than the reference voltage Vref. In response to the signal VCOM from the voltage comparator 5, the switches SW1 and SW2 are controlled for switching. Both switches SW1 and SW2 herein are constructed of a p-channel type switch such as a p-channel MOS transistor.
The output node of the voltage comparator 5 is connected to the connection node 104. The connection node 104 is connected to the gate of the switch SW1 and is also connected to the gate of the switch SW2 via a NOT gate circuit 9. When the voltage comparator 5 outputs an H-level (high level) VCOM signal, the signal is given to the switch SW1, causing it to turn off. At the same time, the switch SW2 receives the inverted signal of VCOM via the NOT gate circuit 9, and then is turned on. On the other hand, when the voltage comparator 5 outputs an L-level (low level) VCOM signal, the switch SW1 is turned on and the switch SW2 is turned off. Namely, when the voltage appearing at the connection node 105 is lower than the reference voltage Vref, the voltage comparator 5 outputs the H-level VCOM signal, causing the switch SW1 to turn off and the switch SW2 to turn on, and the battery power supply voltage supplied at the main battery power supply voltage node 102 connected to the first battery BAT 1 (or at the auxiliary battery power supply voltage node 103 connected to the second battery BAT 2 when the first battery BAT 1 is not present) is fed to the internal power supply voltage node 8. When the voltage appearing at the connection node 105 is higher than the reference voltage Vref, the voltage comparator 5 outputs the L-level VCOM signal causing the switch SW1 to turn on and the switch SW2 to turn off at the same time, and the external power supply voltage supplied at the external power supply voltage node 101 is fed to the internal power supply voltage node 8.
FIG. 9 shows the construction of another known portable-type semiconductor memory device 1A. Since in the known semiconductor memory device 1 in FIG. 8 the first battery BAT 1 works as the charging power supply for the second battery BAT 2 that is the auxiliary battery, the consumption of the first battery BAT 1 is disadvantageously expedited. In this known example, therefore, the second battery BAT 2 as the auxiliary battery is charged by a charging circuit 6 to be described later which is driven by the external power supply voltage supplied via the external power supply voltage node 101 connected to the power supply VCC in the host apparatus 2 as the external power supply. In this example, the second battery BAT 2 is connected, via a switch SW4, to the charging circuit 6 driven by the power supply VCC in the host apparatus 2. When the external power supply voltage supplied at the external power supply voltage node 1 by the power supply VCC is higher than a predetermined value, the charging circuit 6 charges the second battery BAT 2 with the external power supply supplied via the external power supply voltage node 101.
As FIG. 10 shows an example, the charging circuit 6 comprises: an npn transistor 6e with its collector connected to the external power supply voltage node 101, its base connected to a connection node 62, and its emitter connected to an output node 61; a resistor 6a connected between the output node 61 and a connection node 63; a resistor 6b connected between the connection node 63 and ground node; a constant current source 6f connected between the external power supply voltage node 101 and the connection node 62 to which the base of the npn transistor 6e is connected; an npn transistor 6d with its collector connected to the connection node 62 and its base connected to the connection node 63; and a resistor 6c connected between the emitter of the npn transistor 6d and the ground node. The operation of the charging circuit 6 is now discussed. The constant current source 6f presents a constant voltage VBE between the base and emitter of the npn transistor 6d. When a resistance value of the resistor 6c is set so that a value of the voltage drop across the resistor 6c is equal to a value of the voltage VBE, the resistor 6c offers a zero temperature coefficient. Therefore, the voltage appearing at the connection node 63 is a constant voltage that is less temperature-dependent. By magnifying this through resistors 6a and 6b, a constant voltage of 3 V to be used as battery charging voltage appears at the connection node 61. Since the second battery BAT 2 is provided with the charging circuit 6, the main battery power supply voltage node 102 and the auxiliary battery power supply voltage node 103 are connected to the internal power supply voltage node 8 via separate switches SW2 and SW3, respectively. The rest of the construction remains unchanged from that in FIG. 8, and those component equivalent to those with reference to FIG. 8 are designated with the same reference numerals and their explanation will not be repeated.
In this known example, the gates of the switches SW2 and SW3 are connected, through the NOT gate circuit 9, to the connection node 112 that is connected to the output node of the voltage comparator 5. When the voltage comparator 5 outputs a VCOM signal, an inverted VCOM signal is input to the switches SW2 and SW3. On the other hand, the gates of switches SW1 and SW4 are directly connected to the connection node 112 that connects to the output node of the voltage comparator 5, and thus, the VCOM signal is fed to them, as it is. Since these switches SW1, SW2, SW3 and SW4 are all constructed of p-channel MOS transistors, the switches SW1 and SW4 are turned off with the switches SW2 and SW3 turned on when the voltage comparator 5 outputs the H-level VCOM signal. When the voltage comparator 5 outputs the L-level VCOM signal, the switches SW1 and SW4 are turned on with the switches SW2 and SW3 turned off. The voltage comparator 5 herein outputs the L-level VCOM signal when the voltage at the connection node 105 given by the resistors R1 and R2, that voltage divide the external power supply voltage supplied at the external power supply voltage node 101, is higher than the reference voltage Vref. On the other hand, the voltage comparator 5 outputs the H-level VCOM signal when the voltage at the connection node 105 is lower than the reference voltage Vref.
In the known example as shown in FIG. 9, when the portable-type semiconductor memory device 1A is connected to the host apparatus 2, namely when the voltage appearing at the connection node 105 is higher than the reference voltage Vref, the switch SW1 is turned on. The power supply VCC feeds the voltage to the internal power supply voltage node 8 so that data stored in the memory 3 is held. At the same time, the switch SW4 is turned on, causing the second battery BAT 2 to be charged by the charging circuit 6 driven by the power supply VCC. On the other hand, when the power from the power supply VCC is interrupted when the portable-type semiconductor memory device 1A is disconnected from its host apparatus 2, namely when the voltage appearing at the connection node 105 is lower than the reference voltage Vref, the voltage comparator 5 gives the output signal VCOM that causes the switches SW1 and SW4 to turn off and the switches SW2 and SW3 to turn on. The first and second batteries BAT 1 and BAT 2 feed the power to the internal power supply voltage node 8 for the memory 8 to hold data, via the main battery power supply voltage node 102 and the auxiliary battery power supply node 103, respectively.
As has been described above, in the known example in FIG. 8, the first battery BAT 1 which serves as the main battery works as the charging power supply for the second battery BAT 2 serving as the auxiliary battery BAT 2. In such an arrangement, the first battery BAT 1 is consumed rapidly, thereby shortening the life of the first battery BAT 1 and leading to premature replacement.
In the known example in FIG. 9, since the second battery BAT 2 is charged by the charging circuit 6 driven by the power supply VCC in the host apparatus 2, such an inconvenience as rapid consumption of the first battery BAT 1 experienced in the example in FIG. 8 will not take place. When the portable-type semiconductor memory device 1A as shown in FIG. 9 is disconnected from the host apparatus 2, power of both the first battery BAT 1 and the second battery BAT 2 is consumed at the same rate for the memory 3 to hold data. The second battery BAT 2 may be already fully consumed when it is needed most, namely during the replacement of the first battery BAT 1. Data holding by the memory 3 thus may not be properly performed and the loss of data may take place.
In the known device in FIG. 9, therefore, the second battery BAT 2 should be of a relatively large capacity, and thus a small battery cannot be used. As a result, the unit becomes bulky. Since in both known devices 1 and 1A in FIGS. 8 and 9, a chemical battery is employed as the second battery BAT 2, the second battery BAT 2 has its limitation in charge and discharge cycles and is subject to aging and liquid leakage problems. In view of these, a battery holder is included to assure the replacement of the battery. This makes the device even bulkier, and complicates manufacturing steps, and increases manufacturing costs.